We are looking forward to working with a bright and passionate engineer, specialized in either Physical Design Implementation or Timing-related Checks at Hanoi.

Your Role

Key responsibilities in your new role

• Be responsible for planning and execution of either of two areas, based on the competency:
• All aspects of Physical Design Implementation including Synthesis, Floorplanning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification using EDA tool chain - FusionCompiler - with the low power design (preferred)
• Timing Related Checks which include Timing Fixture, Hold & Setup Requirement, DRV checks, Power Intent spec and checks and all Signoff Checks
• Support the schedule and plan arrangements to meet project milestones deadlines, aligning with the other cluster designer, reporting regularly to project manager the status of the entire layout development
• Automate design work by means of script programming (e.g. Tcl/tk, Python)
  

Your Profile

Qualifications And Skills To Help You Succeed

• Bachelor's Degree or above in Digital Design or any relevant field
• 3+ years of hands-on experience in Floorplanning, Place and Route, Clock Tree Synthesis, Physical Verification Error Fixing, or Logic Synthesis
• Understanding of timing constraints, Static Timing Analysis and timing sign-off conditions
• Understanding of IREM flow and Multiple power domain design flow
• Deep understanding of scripting languages (Shell, Perl, Tcl and Python) and Make flow
• Capability to drive ambitious schedules and enable dependent teams to accomplish
• Self-motivated mindset and initiatives to drive new methodologies
  
  

Contact:

Nathan.Kim@infineon.com

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Are you in?

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