Principal Engineer Package Development

Infineon Technologies

Infineon Technologies

Shanghai, China

Posted on Mar 21, 2026
Your Role

Key responsibilities in your new role

  • Responsible for technical support of new product/package/new process development
  • Ensure that the project meets customer requirements in terms of timeline, cost and quality
  • Assess and mitigate technical risks
  • Provide design proposal for package, lead frame, substrate and Cu-clip of new products
  • Close interaction with the project manager, subcon interface, chip designer, application team, marketing and business units for new product design and project roadmaps
  • Provide technical direction related to problem solving of process and reliability issues
  • Closure of Package Development related deliverables and documents
  • Technical Documentation thru Delta analysis DFMEA, PFMEA, Process Flow& Control plan

Your Profile

Qualifications And Skills To Help You Succeed

  • Master / Bachelor Degree in Engineering and Physical Science
  • Minimum requirement 5 Years of Package/Process development in Semiconductor packaging
  • Experience in analytical tools: Delta Analysis, DFMEA, DoE, 8D and simulation.
  • Proficient in AutoCAD for 2D drawing. Knowledge using 3D software(e.g. AutoCAD 3D, Inventor, and SolidWorks) is an advantage
  • Exposure to the development of a wide variety of packages: TO, QFN, CuClip, Flip Chip, SOIC, QFP
  • Knowledge in package design rules, FA techniques, assembly processes, IP management and patent filing
  • Proficient in industry standards for package reliability test and qualifications
  • Can interpret package simulation results. Knowledge in package simulation software (e.g. ANSYS, SolidWorks) for FEA & thermal analysis is an advantage
  • Excellent in statistical analysis that can provide a clear direction based on package/process DOE
  • Working knowledge of DFMEA during design phase and ability to create strategy to mitigate risk

Contact:

lucy.shi@infineon.cn

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