We are looking forward to working with a passionate engineer in the field of Digital Functional Verification, to be responsible for developing SV-UVM based environments.

Your Role

Key responsibilities in your new role

• Be in charge of the development and maintenance of robust SV-UVM based verification environments.
• Develop and execute comprehensive verification plans to ensure maximum design coverage.
• Debug complex test failures and perform deep-dive root-cause analysis.
• Monitor and report real-time verification status and progress to stakeholders.
• Evaluate verification regressions and drive high-quality deliveries through rigorous testing.
• Collaborate with design teams to resolve architectural and RTL-level issues.
  
  

Your Profile

Qualifications And Skills To Help You Succeed

• Degree in Electrical/Electronic Engineering, Computer Science, or a related field.
• Fluent English communication skills for effective global collaboration.
• Strong understanding of Digital Design concepts, and verification tools and flows.
• Hands-on experience or academic project exposure to SystemVerilog (SV) and UVM.
• Knowledge of Firmware and RTL design is a significant plus.
  
  

Contact:

Nathan.Kim@infineon.com

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