Siemens EDA is a global technology leader in electronic design automation software. Our software tools enable companies around the world to develop new and highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics in order to deliver better products in the increasingly complex world of chip, board and system design.

Position Overview

The Tessent division seeks a highly motivated, creative, and energetic individual as Product Engineer, specializing in design-for-test (DFT) and test delivery at chip and system level. Tessent is the market and technology leader of automated tools for insertion of semiconductor design-for-test (DFT) structures, automatic test pattern generation (ATPG), embedded deterministic compression (EDT), memory built-in self-test (MBIST), logic built-in self-test (LBIST), diagnosis-driven yield analysis (DDYA), hierarchical DFT solutions such as Streaming Scan Network (SSN), and analog fault injection and test. This position presents a great opportunity to stay involved technically while getting exposure to marketing and interacting with sales.

Responsibilities include but are not limited to:

• Define and characterize new product capabilities needed to meet customer requirements
• Work collaboratively with Tessent R&D to prototype, evaluate, and test new products and features within complex IC design flows
• Lead beta programs and support beta partners
• Drive product adoption and growth
• Create and deliver in-depth technical presentations, develop training material, white papers, contributed articles, and application notes
• Develop and review tool documentation such as user and reference manuals
• Work with customers as well as Siemens EDA stakeholders such as regional application engineers, global support engineers, and marketing
• Work through complex technical issues and independently create solutions and new methodologies
• Present complex principles in simple terms to broad audiences
• Collaborate and share information across team boundaries in written and spoken forms
• Some travel, domestic and international

Job Qualifications

The successful candidate will possess the following combination of education and work experience:

• BS degree (or equivalent) in Electrical Engineering, Computer Science, Computer Engineering, or related field is required
• Must have minimum 8 years of experience, including 3+ years of experience in DFT for complex ASICs / SOCs, including some of the following areas: Automatic test pattern generation (ATPG), internal scan, embedded scan compression (EDT), packetized test delivery (SSN), memory built-in self-test (MBIST), logic built-in self-test (LBIST), IEEE 1687 IJTAG, analog design and simulation, hierarchical DFT implementation
• Must have industry experience with DFT tools, preferably Tessent tool suite such as TestKompress, SSN, IJTAG, In-system Test
• Able to architect Design for Test solution for every aspect of complex IC SoC design, including but not limited to hierarchal or tiled designs, designs with multiple power domains and high-speed IO IP
• Industry experience with inserting scan, running ATPG and debugging fault coverage
• Industry experience with the application of logic test patterns on Automatic Test Equipment (ATE) and creation of test program
• Knowledge of IG-XL, Smartest8, Python or bench environments for production test or characterization
• Exposure to one or more adjacent IC disciplines such as the following a plus:
  • RTL coding and verification using Verilog/SystemVerilog/VHDL
  • Synthesis and timing analysis
  • Place and route
  • Advanced IC packaging
  • DFT and test for embedded IP cores
  • Failure diagnosis
  • ATE use / test program development
• Candidate should be high energy, curious individual, self-motivated to learn new DFT methodologies and technologies
• Able to work as individual contributor and lead technical activities of junior engineers
• Strong problem-solving, reasoning and deduction skills and the ability to analyze and debug complex design and simulation issues
• Proficiency in LINUX and Windows environments
• Proficiency in a scripting language like TCL (preferred) or Python
• Excellent written and spoken English language communication skills
• Excellent organizational skills
• Nice to have skills:
  • Knowledge of HSIO functional interfaces such as PCIe or USB and their usage for DFT
  • Knowledge of functional verification techniques using UVM, PSS, emulators and VIP
  • Experience with sensors/monitors for IC designs that provide process, voltage, temperature, and other monitoring
  • Experience with application of patterns in a System Level Test (SLT) environment
  • Industry experience with FPGA design development and prototyping
  • Knowledge of data bases, visualization tools and packages
• Location can be remote or hybrid in North America, or in-office at one the following Tessent locations:
  • Wilsonville (Oregon), Ottawa (Canada), Saskatoon (Canada), Fremont (California)

Equal Employment Opportunity Statement
Siemens is an Equal Opportunity and Affirmative Action Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to their race, color, creed, religion, national origin, citizenship status, ancestry, sex, age, physical or mental disability unrelated to ability, marital status, family responsibilities, pregnancy, genetic information, sexual orientation, gender expression, gender identity, transgender, sex stereotyping, order of protection status, protected veteran or military status, or an unfavorable discharge from military service, and other categories protected by federal, state or local law.

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